Verilog HDL高级数字设计（第二版）（英文版）
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作者： （美）西勒提 著
出 版 社： 电子工业出版社
出版时间： 2010-4-1字数： 1813000版次： 1页数： 965印刷时间： 2010-4-1开本： 16开印次： 1纸张： 胶版纸I S B N ： 9787121104770包装： 平装
本书依据数字集成电路系统工程开发的要求与特点，利用Verilog HDL对数字系统进行建模、设计与验证，对ASIC/FPGA系统芯片工程设计开发的关键技术与流程进行了深入讲解，内容包括：集成电路芯片系统的建模、电路结构权衡、流水、多核微处理器、功能验证、时序分析、测试平台、故障模拟、可测性设计、逻辑综合、后综合验证等集成电路系统的前后端工程设计与实现中的关键技术及设计案例。书中以大量设计实例叙述了集成电路系统工程开发需遵循的原则、基本方法、实用技术、设计经验与技巧。
本书既可作为电子与通信、电子科学与技术、自动控制、计算机等专业领域的高年级本科生和研究生的教材或参考资格，也可用于电子系统设计及数字集成电路设计工程师的专业技术培训。
Michael D.Ciletti，科罗拉多大学电气与计算机工程系教授。研究方向包括通过硬件描述语言进行数字系统的建模、综合与验证、系统级设计语言和FPGA嵌入式系统。其著作还有Digital Design，Fourth Edition(其翻译版和影印版均由电子工业出版社出版)。作者曾在惠普、福特微电子和Prisma等公司进行VLSI电路设计的研发工作，在数字系统和嵌入式系统研究、设计等领域有丰富的研发和教学经历。
1 Introduction to Digital Design Methodology
1.1 Design Methodology—An Introduction
1.2 IC Technology Options
1.3 Overview
References
2 Review of Combinational Logic Design
2.1 Combinational Logic and Boolean Algebra
2.2 Theorems for Boolean Algebraic Minimization
2.3 Representation of Combinational Logic
2.4 Simplification of Boolean Expressions
2.5 Glitches and Hazards
2.6 Building Blocks for Logic Design
References
Problems
3 Fundamentals of Sequential Logic Design
3.1 Storage Elements
3.2 Flip-Flops
3.3 Busses and Three-State Devices
3.4 Design of Sequential Machines
3.5 State-Transition Graphs
3.6 Design Example: BCD to Excess-3 Code Converter
3.7 Serial-Line Code Converter for Data Transmission
3.8 State Reduction and Equivalent States
References
Problems
4 Introduction to Logic Design with Verilog
4.1 Structural Models of Combinational Logic
4.2 Logic System, Design Verification, and Test Methodology
4.3 Propagation Delay
4.4 Truth Table Models of Combinational and Sequential Logic with Verilog
References
Problems
5 Logic Design with Behavioral Models of Combinational and Sequential Logic
5.1 Behavioral Modeling
5.2 A Brief Look at Data Types for Behavioral Modeling
5.3 Boolean Equation-Based Behavioral Models of Combinational Logic
5.4 Propagation Delay and Continuous Assignments
5.5 Latches and Level-Sensitive Circuits in Verilog
5.6 Cyclic Behavioral Models of Flip-Flops and Latches
5.7 Cyclic Behavior and Edge Detection
5.8 A Comparison of Styles for Behavioral Modeling
5.9 Behavioral Models of Multiplexers, Encoders, and Decoders
5.10 Dataflow Models of a Linear-Feedback Shift Register
5.11 Modeling Digital Machines with Repetitive Algorithms
5.12 Machines with Multicycle Operations
5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?
5.14 Algorithmic State Machine Charts for Behavioral Modeling
5.15 ASMD Charts
5.16 Behavioral Models of Counters, Shift Registers, and Register Files
5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals
5.18 Design Example: Keypad Scanner and Encoder
References
Problems
6 Synthesis of Combinational and Sequential Logic
7 Design and Synthesis of Datapath Controllers
8 Programmable Logic and Storage Devices
9 Algorithms and Architectures for Digital Processors
10 Architectures for Arithmetic Processors
11 Postsynthesis Design Tasks
A Verilog Primitives
B Verilog Keywords
C Verilog Data Types
D Verilog Operators
E Verilog Language Formal Syntax
F Verilog Language Formal Syntax
G Additional Features of Verilog
H Flip-Flop and Latch Types
I Verilog-2001, 2005
J Programming Language Interface
K Web sites
L Web-Based Resources
Index
